Assertion-level Proof Representation with Under-Specification

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Assertion-level Proof Representation with Under-Specification

We propose a proof representation format for human-oriented proofs at the assertion level with under-specification. This work aims at providing a possible solution to challenging phenomena worked out in empirical studies in the DIALOG project at Saarland University. A particular challenge in this project is to bridge the gap between the human-oriented proof representation format with under-spec...

متن کامل

Assertion level proof planning with compiled strategies

The objective of this thesis is to ease the formalization of proofs by being able to verify as well as to automatically construct abstract human-style proofs. This is achieved by lifting the logical basis to the abstract assertion level, which has been identified as a style of reasoning that can be found in textbooks. A case study shows that automatic reasoning procedures benefit from the abstr...

متن کامل

PSL Assertion Checking with Temporally Extended High-Level Decision Diagrams

The paper proposes a novel method for PSL language assertions conversion to a system representation model called High-Level Decision Diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. We present a technique, where checking of PSL assertions is integrated into fast HLDDbased simulation. There are three main contribu...

متن کامل

Assertion Checking with PSL and High-Level Decision Diagrams

The paper proposes a novel method for checking PSL language assertions using a system representation called HighLevel Decision Diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and test pattern generation. We present a technique, where checking of PSL assertions is integrated into fast HLDD-based simulation. Current approach applies assertion checker ge...

متن کامل

Foundations of the Trace Assertion Method of Module Interface Specification

The trace assertion method is a formal state machine based method for specifying module interfaces. A module interface specification treats the module as a black-box, identifying all module’s access programs (i.e. programs that can be invoked from outside of the module), and describing their externally visible effects. In the method, both the module states and the behaviors observed are fully d...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Electronic Notes in Theoretical Computer Science

سال: 2004

ISSN: 1571-0661

DOI: 10.1016/j.entcs.2003.12.026